Oversampled ADC based on pulse frequency modulator and TDC

Oversaw led converters based on voltage controlled ring oscillators are an attractive solution because of their digital implementation and simplicity. However, the voltage-to-frequency conversion of ring oscillators displays a poor linearity. Replacing the ring oscillator by a pulse frequency modulator (PFM) that provides improved linearity at the expense of feedback and analogue amplification is proposed. Compared to the equivalent continuous time sigma delta modulators, the PFM may be more tolerant to circuit impairments. In addition, the output data of the proposed architecture is a multibit sequence through the use of a time-to-digital converter TDC instead of a Flash quantiser or a multibit digital-to-analogue converter. A high dynamic range can be achieved without severe constraints on analogue mismatch or clock jitter

Analytical Evaluation of VCO-ADC Quantization Noise Spectrum Using Pulse Frequency Modulation

Oversampled ADCs based on voltage-controlled oscillators have been analyzed using statistical models inherited from sigma-delta modulation. This letter shows that the discrete Fourier transform of a VCO-ADC output sequence can be calculated analytically for single tone inputs. The calculation is based on the transformation of the VCO output into a pulse frequency modulated signal that can be represented by a trigonometric series. Knowledge of the VCO-ADC output spectrum allows accurate evaluation of the SNDR dependence with the VCO oscillation frequency and gain constant. The SNDR predictions of the proposed model have been compared to behavioral simulations displaying only a deviation of 0.7 dBThis work was supported by the CICYT project under Grant TEC2010-16330.Publicad

VCO-based sturdy MASH ADC architecture

A new multistage 1-1 ΔΣ analogue-to-digital converter (ADC) architecture implemented only with voltage-controlled oscillators (VCOs) is introduced. A sturdy multistage noise-shaping (SMASH) configuration is used to avoid the need of either calibration circuitry or noise-cancellation filters. The digital nature of the VCO's output simplifies the implementation of the interconnection paths between stages, making unnecessary neither the use of multibit digital-to-analogue converters nor analogue subtraction elements. The basic operation of the architecture is shown at system level and the sensitivity to VCO's frequency mismatch is analysed. The proposed architecture has been validated through behavioural simulations.This work was supported by the CICYT project TEC2014-56879-R, Spain

High-Speed and Energy-Efficient Ring-Oscillator for Analog-to-Digital Conversion

The aim of this conference is to offer the possibility to present and discuss new research results on the area of integrated circuits and systems and all its fields of application. A major emphasis has been given in the technical program to emerging topics such as electronic systems for artificial intelligence, reliability of circuits and devices, unconventional computing, smart sensors and other relevant topics. The conference on Design of Circuits and Integrated Systems (DCIS) is an international meeting for researchers in the highly active fields of micro- and nano-electronic circuits and integrated systems. It provides an excellent forum to present and discuss works on the emerging challenges offered by technology, in the areas of modeling, design, implementation and test of devices, circuits and systems. The 35th edition will be organized by Universidad Politécnica de Madrid

Resolution Enhancement of VCO-based ADCs by Passive Interpolation and Phase Injection

Proceeding of: 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS), 20-22 November 2019, Bilbao, SpainThis work describes a simple way to improve the resolution of low-pass voltage-controlled-oscillators based analog-to-digital converters (VCO-based ADCs) implemented with ring-oscillators. We propose to insert a passive resistive network into the differential delay cells of the oscillator to get additional interpolated phases. These interpolated phases are then injected to other similar oscillators. By increasing the number of phases coming from all the oscillators, the effective gain of the system is higher and enhances the resolution of the converter. To validate the idea, a prototype of an open-loop VCO-based ADC was built in VerilogA language with ring-oscillators designed with a 65-nm CMOS process. The results of transient simulations were compared to the results of a behavioral ideal model of the system built in MATLAB. As expected, the signal-to-noise ratio (SNR) was improved in concordance with the increase in the number of phases. Finally, it was checked that the proposed circuit used to extract and inject the interpolated phases did not penalize the total power consumption. The proposed circuit structure is particularly suitable for high-bandwidth applications, where the oversampling ratio (OSR) is strongly restricted and the gain is limited because of the oscillator non-linearity. Due to the highly digital nature of the VCO-based ADC structures, this solution may be of special interest to be implemented in new deep-submicron CMOS processes.This work was supported by the CICYT project TEC2017-82653-R, Spain.Publicad

Analysis of in-band spurious tones of VCO-based analog filters and mitigation techniques

Proceedings of: 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 21-25 May 2023, Monterey, USA.Recently VCO-based filters have been used to implement feature extraction in voice recognition systems. Typically implemented filter structures embed the VCOs in a feedback loop. In these implementations, harmonic distortion has been observed in the output signal. This harmonic distortion has been attributed to ring oscillator nonlinearity but its origin stems from a system level problem. In this manuscript we will analyze this problem by looking at the cross modulation of Pulse Frequency Modulation (PFM) side-bands and we will explain how this creates the previously misunderstood harmonic distortion. Moreover, we will propose efficient techniques to mitigate these harmonic components and show that they can easily be implemented in hardware.This paper was supported by program H2020-MSCA-ITN-2020 grant Nr. 956601 and project PID2020-118804RB-I00 of the Spanish Agency of Research (AEI) and by FWO-Vlaanderen

VCO-based ADC with a simplified DAC for non-linearity correction

The performance of open-loop ADCs implemented with VCOs is limited by VCO non-linearity and first-order noise shaping. The resolution limitation imposed by first-order noise shaping can be compensated by a ring oscillator VCO with many output phases. Linearity can also be improved by using a feedback loop around the VCO closed with a DAC. However, a long ring oscillator may require a DAC with a prohibitive number of bits if feedback is used to compensate distortion. This Letter proposes an ADC architecture based on the Leslie-Singh Sigma-Delta (Σ∆) modulator that allows to implement a distortion correction loop around a VCO with a simplified DAC of few levels, yet keeping a large number of output quantisation levels to maintain resolution. The Letter discusses the system-level architecture and shows an implementation circuit example to verify the effective correction of distortion.This work has been supported by the CICYT project TEC2014-56879-R, Spain

Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs

Proceeding of: 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS): August 9-12, 2020, Springfield, MA, USA: on-line proceedings.A new phase-encoded MAC cell is proposed for low power smart sensing applications. If digitization of the raw data is made through voltage-controlled-oscillators based analog-to-digital converters (VCO-based ADCs), we may take the unsampled frequency-encoded output signal and connect it to the first layer of a neural network. Then that layer could be implemented with phase-encoded MAC accelerators, leading to an energy-efficient solution. The MAC cell does not only make the accumulation/subtraction and multiplication operation, but also the non-linear function which supposes a great advantage with respect to other equivalent cells. A circuit example is proposed in a 65-nm CMOS process and transient simulations prove the feasibility of the approach.Publicad

A Time-Encoded Capacitance-to-Digital Converter Based on a Switched-Capacitor Feedback

An innovative method to perform capacitance-to-digital conversion without requiring sensor biasing circuitry is proposed. This letter is intended for the readout of MEMS capacitive microphones used in human-to-machine interface applications, where the main constraints are low power consumption and small chip area. The time-encoded sigma-delta ADC described here employs a switched-capacitor-based feedback to linearize the voltage-controlled oscillator and to couple the capacitive sensor to the readout. A prototype was fabricated to test the concept with a CMOS 130-nm process. The achieved relative capacitance resolution is 14.7 b with a rest capacitance value of 2.575pF and a total power consumption of 343μW . Linearity measurements ( SNDRpeak=51.5 dB in the bandwidth from 300Hz to 6.8kHz ) are limited by the test fixture due to the nonlinearity of the varactor introduced in lieu of a testing input sensor.The project funded from the European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement No. 956601, involves the collaboration between Universidad Carlos III de Madrid and Infineon Technologies AG Austria

A VCO-based CMOS readout circuit for capacitive MEMS microphones

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered 'always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta (SigmaDelta) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1/𝑓 and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 muA at 1.8 V and the effective area is 0.12 mm2. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.This research was funded by project TEC2017-82653-R of CICYT, Spain